FPGA Design & Verification
DO-254 / Safety Critical
Hardware Assisted Verification
ASIC Design & Verification
Public VHDL Training
Online VHDL Training
Work for Us
FirstEDA Insights Blog
Code Coverage and Functional Coverage – What’s the Difference?
Achieving Better Coverage with VHDL - Part 1
Jim Lewis Blog - OSVVM gone Apache … on the path to IEEE Open Source
An Introduction to Assertion-Based Verification - Part 2
Linting vs. Design Rule Checking - What’s the difference?
Agnisys Blog Post - Repurposing von Neumann Architecture with SRAM-based Register Files
An Introduction to Assertion-Based Verification - Part 1
OneSpin Blog - OneSpin Users Gather In Munich
OneSpin Blog - CEO Perspective - Innovation Requires IC Integrity
Aldec Blog - Evaluating NVMe SSD Multi-Gigabit Performance using Aldec TySOM-3/3A Boards
Aldec Blog - When is robustness verification DO-254 projects complete?
Aldec Blog - How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices
Agnisys Blog Post - Register Automation using Machine Learning
Agnisys Blog Post - Setting the Stage for the Next Abstraction
VHDL Training with a difference
Agnisys Blog Post - Creating Test Sequences for RISC-V Cores and SoCs
Aldec Blog Post - HW/SW Co-Verification Environment for Hybrid Systems Using QEMU
Jim Lewis Blog - OSVVM at #DVConEurope
Aldec Blog Post - Unit Linting: An easy way to prevent code review issues
Aldec Blog Post - Trace Your Assertions
Aldec Blog Post - Do I really need a commercial simulator?
Aldec Blog Post - HW/SW Co-Simulation for SoC FPGA designs
Aldec Blog Post - FPGA vs GPU for Machine Learning Applications: Which one is better?
Aldec Blog Post - Problems Accessing Registers? – See how UVM RAL can help.
Jim Lewis - OSVVM, The #1 VHDL Verification Library
Sigasi - Hardware Design Made Easier, More Efficient And More Fun
Design Rule Checking – How Early is Early?
Aldec Blog Post - 35-years-old, and still on point
Time flies when you’re having fun
Aldec Blog Post - No Risk No Fun.
Earning my stripes at my first industry conference
FirstEDA Verification Series - Code Coverage
Design Rule Checking comes of age
Constrained random testing - the magic bullet?
The case for running equivalence checking on your FPGA
OSVVM User Group meeting at DAC
The value of the right text editor?
Copyright © 2002-2020 FirstEDA Limited. All Rights Reserved.