FPGA Design & Verification
DO-254 / Safety Critical
Hardware Assisted Verification
ASIC Design & Verification
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FirstEDA Insights Blog
Aldec Blog Post - Unit Linting: An easy way to prevent code review issues
Aldec Blog Post - Trace Your Assertions
Aldec Blog Post - Do I really need a commercial simulator?
Aldec Blog Post - HW/SW Co-Simulation for SoC FPGA designs
Aldec Blog Post - FPGA vs GPU for Machine Learning Applications: Which one is better?
Aldec Blog Post - Problems Accessing Registers? – See how UVM RAL can help.
Jim Lewis - OSVVM, The #1 VHDL Verification Library
Sigasi - Hardware Design Made Easier, More Efficient And More Fun
Design Rule Checking – How Early is Early?
Aldec Blog Post - 35-years-old, and still on point
Time flies when you’re having fun
Aldec Blog Post - No Risk No Fun.
Earning my stripes at my first industry conference
FirstEDA Verification Series - Code Coverage
Design Rule Checking comes of age
Constrained random testing - the magic bullet?
The case for running equivalence checking on your FPGA
OSVVM User Group meeting at DAC
The value of the right text editor?
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