By Nomita Goswami, Applications Specialist, FirstEDA
Are you a UVM Verification Engineer? Does your design have a large number of registers that need to communicate between hardware and software interfaces?
Being involved in creating UVM Environment test benches means you would have realised that writing all the SystemVerilog and testbench code by hand is a gruesome task. It is tempting to automate your work as much as possible, and with the UVM Register model being a considerable part of your design, you would love the idea of generating synthesisable models and UVM Verification components for it.
And if you knew you could generate all this using your Specification, then that would be the icing on the cake!
The registers and memories can be defined using IP-XACT or a register definition language such as SystemRDL, and IDesignSpec can generate a UVM RAL model from these specifications. A simple, abstract input file can produce complex SystemVerilog code to define and instantiate the registers and memories.
For users who prefer a graphical specification, Agnisys provides plug-ins for Microsoft Word (as shown below), Microsoft Excel, and OpenOffice as well as the IDS-NG cross-platform GUI. Register specification becomes a simple matter of filling out entries in a form, with IDesignSpec doing the rest of the work.
Furthermore, it allows you to generate the whole UVM environment for the testbench. All this on a click of a button!
It also allows you to integrate your code and any third-party IPs that you wish to incorporate, making the whole verification process less daunting and cumbersome for a Verification Engineer. If any changes are required; then the Specification can be updated, and these changes permeate to all the views that IDesignSpec generates hence allowing correct by construction SystemVerilog UVM Testbenches.