Packing my warm gear and heading North for the first FPGA networking event of the year

Last month I took the opportunity to embark on my first international business trip. For someone like me, who for various reasons has not travelled much previously, this was a very exciting prospect. FirstEDA have participated in the annual FPGA-forum conference in Trondheim many times before and, after taking a break in 2017, were looking forward to returning this year. As always, it’s a chance to reintroduce ourselves to old contacts, meet valued customers face-to-face and hopefully create new relationships and opportunities.


As the name suggests, FPGA-forum is a conference for the Norwegian FPGA community. With an organising committee made up primarily of FPGA engineers and with ties to NTNU, this event packs two days of presentations and an exhibition into a full programme. With a focus on methodology and practical experience, it attracts a good mix of attendees, including professionals and academics.


Following a recent release of ALINT-PRO, our Advanced Design Rule Checking (DRC) tool from Aldec, we invited their product manager, Sergei Zaychenko, to join us and present on ‘Dealing with CDC verification complexity in large-scale FPGA designs’. We also signed up to exhibit, which as a salesman who spends most of my time speaking to customers on the phone or via email, was another thing I was particularly looking forward to.


The conference was well attended, with nearly 120 participants, together with representatives from many partner companies. The presentations were arranged across two separate tracks, with Sergei presenting on the first day to a full room (apologies to whoever was presenting to themselves next door!). As my first conference, I must say I was impressed at how organised the whole event was. In the exhibition area I had plenty of opportunities to speak to attendees and discuss their challenges and requirements.


Common themes over the two days were deep learning, artificial intelligence and consequently many of the presentations and keynotes were geared around them. Regardless of what market you currently target, these topics appear relevant to all, and bring with them a host of new engineering challenges. Driven by the need to process huge quantities of data, FPGA engineers now require more powerful tools, complimentary agile approaches and smarter ways of working. VHDL is clearly still the primary design language (no surprise to us!) and much of my time was spent discussing methodology and tools that can benefit the VHDL design and verification process.


On a related note, I was surprised at how many companies expect their engineers to work on bleeding edge technology, with ever growing designs, without investing in fit-for-purpose tools and training. There is no denying that the vendor supplied tools are more capable than ever but there inevitably comes a point when they simply run out of steam. Of course, it’s inbuilt for engineers to work with limited resources but sometimes I can’t help but think that you make it difficult for yourselves!


I also find that those who have invested in tools are often not satisfied with the level of VHDL support available to them. At the event I witnessed an engineer enquiring with their tools distributor (not FirstEDA!) about their VHDL roadmap, only to be told that they should move to SystemVerilog; and this was after he had spent ten minutes explaining how important VHDL was to them! I am not an engineer myself, so I don’t have a first-hand perspective on this, but from the conversations that I had at FPGA-forum (and on a daily basis) I can appreciate that it would be frustrating feeling ‘forced’ away from a language that you and your team have extensive experience with.


Thankfully this is no issue for our customers because, as a European company supporting European FPGA teams, we understand the significance of VHDL, as it continues to be the most common design language. Through our partners at Aldec and Sigasi, we provide tools with class-leading VHDL language support; they are also actively involved in the VHDL standardisation effort and contribute to the continued development of the language. Through our training business we also demonstrate how to get the most out of VHDL for verification too. The bottom line is that you must be willing to invest. We all know that schedule slippage can be costly. A few hours spent upfront discussing your challenges, or a few days spent on a training course, may initially seem difficult to justify, but the benefits of becoming more efficient as a result will surely pay dividends in the long term. Hopefully, those people that I did get the opportunity to speak to at FPGA-forum, will soon start to benefit as we progress the follow-on tool evaluations and they join us on our training courses.


In summary, I very much enjoyed my time in Norway, not least because FPGA-forum was interesting, but also the people I met were open & friendly, the beer was cold & plentiful and, despite being jaw-dropping expensive, the food was incredible!


FirstEDA are returning to Scandinavia in May for our next 5-day ‘Advanced VHDL Testbenches and Verification’ training course, hosted in Gothenburg and, as always, delivered by OSVVM architect Jim Lewis. Hopefully we will get the opportunity to meet you too, to assist in easing your VHDL design and verification challenges. Full details of the course can be viewed on the FirstEDA website here,