Blog: Jim Lewis Blog – OSVVM at #DVConEurope

Getting ready to present my paper, Transaction-Based Testing with OSVVM and the OSVVM Model Library at #DVConEurope this morning
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DVCon Europe finishes my three week Europe trip this fall. I started with teaching our OSVVM class in Bracknell, UK in conjunction with our partner FirstEDA. The following week I taught our OSVVM class in Freiburg, Germany in conjunction with our partner PLC2.

It has been a great fall for OSVVM. When I finish November, I will have taught 6 class session, 4 in US and 2 in Europe. This further confirms the Wilson Verification Survey 2018 that OSVVM is the market leading VHDL Verification Solution.

If you missed our current class sessions, in conjunction with FirstEDA, I will be returning to Bracknell in March and June 2020. If you want OSVVM classes in German, be sure to contact our partner PLC2 as my colleague, Patrick Lehmann, has been both teaching OSVVM and using it on their customer projects. SynthWorks also offers all of our classes as an on-line class and will be announcing our 2020 class dates soon.

Looking for a advanced verification solution for your VHDL projects, Open Source VHDL Verification Methodology (OSVVM) is the right answer. OSVVM provides similar capability provided by other verification solutions (such as SystemVerilog + UVM), such as transaction based framework, Constrained Random and Intelligent Coverage Random test methodologies, Functional Coverage, advanced error handling and messaging, scoreboards, memory modelling utilities, synchronisation utilities, as well as a growing verification component library – all as open source.

You will find OSVVM on github at: https://github.com/OSVVM